Trends in computing have clearly defined the need for reliability for both commercial and military computing. As software plays an increasing role in computing systems, reliable methods of determining the correct sequencing and integrity of instructions is needed.
Present systems experience large performance degradation in processing throughput when using existing control flow monitor (CFM) and signatured instruction streams (SIS) techniques to monitor the sequencing and correctness of instructions. Because of large processing demands placed on existing processors due to existing CFM and SIS methods, systems needing CFM and SIS features and non-CFM and SIS performance need more expensive, faster processors to meet system requirements.
Some existing systems monitor the sequence of instructions by performing at least two independent operations on an instruction prior to executing the instruction and then comparing the results from each independent operation. A first operation is typically performed for each opcode of each instruction prior to executing instructions (e.g., opcodes) on the target processor. During the first operation, a predetermined bit is typically calculated for each opcode. Each predetermined bit is stored in memory along with the associated opcode. Each predetermined bit represents a parity bit based on the associated opcode and a state variable determined by the processing system which calculates the predetermined bit. Each instruction is typically comprised of an opcode and a predetermined bit. Then, a second operation is performed for each opcode during run-time when the opcode is fetched from memory. Typically, a run-time bit is determined by the second operation. Each run-time bit represents a parity bit based on the associated opcode and a state variable determined by the run-time processing system which calculates the run-time bit. In some systems, the predetermined bit and the run-time bits are compared for each instruction. When the bits compare, the processor continues processing by executing the opcode. When the bits fail to compare, the processor is typically reset or interrupted to allow error detection processing to continue.
A problem in existing systems is the overhead processing associated with determining the run-time bit for an opcode after a program branch. In many existing systems, having a control flow monitor determine a runtime bit after a program branch requires extra program instructions to fetch a fixword from a table of fixwords. Extra program instructions increase the overhead processing associated with determining a run-time bit after a program branch.
Thus, what is needed is an improved system and method having improved processor performance. What is also needed are an improved system and method for verifying a sequence of instructions during run-time of a computer program. Also needed is an improved system and method for determining a run-time bit based on an opcode for a branch instruction.